Samsung is weighing whether to move commodity DRAM and NAND packaging and testing to Vietnam to free its Korean plants for high-bandwidth memory stacking, industry sources told Digitimes and Korea’s DealSite.
The company is chasing a 47% increase in HBM wafer output, from 170,000 wafers to roughly 250,000 per month by the end of 2026. Its HBM4 yield reached about 80% as of August 10, up from below 60% when mass production began in February.
The constraint is physical. Conventional DRAM and NAND packaging takes about 700 process steps, while an HBM stack adds roughly 19 extra materials-engineering steps using entirely different equipment, including through-silicon via formation. Samsung’s Cheonan campus, with its C1, C2 and C3 lines, is at full HBM stacking capacity, leaving no cleanroom floor space without removing commodity packaging lines.
The reported plan is a dual-track strategy: advanced personnel would shift from Cheonan to Onyang’s new HBM facility, while general DRAM packaging moves to Vietnam. Samsung already runs six plants and an R&D center there, and it filed a proposal to build its first dedicated chip test plant in Thai Nguyen province at a cost of about $1.49B. Intel, Amkor and Hana Micron already operate backend plants in the country.
Every wafer redirected to HBM consumes three to four times the resources of a conventional DRAM wafer, and HBM demand is growing about 70% a year. With Samsung and SK Hynix controlling 90% of global HBM output, backend capacity is becoming a battleground in the AI memory race.
