Intel revisits its memory roots to solve the AI bandwidth crunch

CEO Lip-Bu Tan is weighing a return to memory, betting Intel's packaging know-how can ease the bandwidth squeeze in AI systems.

ChipNews Staff
2 Min Read

AI systems are increasingly limited by how quickly data reaches the processor, not by raw compute speed. That reality is pulling Intel back toward memory, a business it abandoned decades ago, and CEO Lip-Bu Tan is pushing the case that the technology no longer deserves its low-margin commodity label.

The company traces its start to 1968, when it sold memory chips for a living. It was only after Japanese rivals squeezed margins that Intel pivoted to microprocessors. Its NAND unit was later sold off. Rebuilding commodity DRAM or NAND production would mean taking on Samsung, SK hynix and Micron at their own game.

Tan’s answer leans on packaging rather than commodity parts. He has floated stacking memory with processors, whether as HBM stacks beside compute tiles, cache or memory dies bonded above logic, or embedded-memory chiplets. Shorter interconnects would attack the data-delivery bottleneck that constrains today’s accelerators.

Intel has the assembly assets to try, including EMIB silicon bridges, EMIB-T through-silicon vias and Foveros Direct hybrid bonding. Seok-Hee Lee, who once led SK hynix, has joined the company, lending the exploration credibility. No product, fabrication plan or commercial timetable has been announced.

Analysts see differentiated cache, stacked-memory or packaging products co-designed with CPU and accelerator roadmaps as the realistic route, not a revival of commodity memory. In the end it is a systems-engineering wager: keep AI processors fed with data.

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