High-bandwidth memory has become the industry’s proving ground for 3D stack testing, as chipmakers race to catch interconnect defects before they reach data centers where field failures carry enormous costs.
An HBM3 module stacks a dozen or more DRAM chiplets on a silicon interposer, linked by through-silicon vias and microbumps. Engineers now spend as much effort testing those buried connections as the memory cells themselves, because the bonds cannot be probed directly once the stack is assembled.
The pressure will only grow: HBM4 is shifting to hybrid bonding, and HBM5 stacks could reach 24 dies, according to Faisal Goriawalla, director of product management at Synopsys. Test development is a major bottleneck, added Quoc Phan of Siemens EDA, since each chipmaker builds its own proprietary fault models and algorithms.
Vendors such as proteanTecs are pushing preventive monitoring that predicts failures in the field, an approach data center operators running large language models increasingly demand. Custom HBM designs tailored to specific accelerators add further complexity to an already crowded test flow.
The lesson from HBM: in the AI memory race, yield and reliability matter as much as density, and the companies that master 3D assembly testing will have a lasting edge.
