The UCIe chiplet standard is coming to AMD’s Versal adaptive processors, opening the family to third-party dies.
The company will add UCIe connectivity to its RF-focused Versal parts first, letting designers attach chiplets from other vendors through the open interface rather than building everything into one monolithic die. AMD describes the interface as delivering multiterabit-per-second aggregate bandwidth inside the package.
The Versal family traces its roots to Xilinx, the FPGA maker AMD absorbed in 2022, and its modular layout lets one product line span jobs from AI inference to radio frequency signal processing. SoC-class Versal options will follow once the market matures, with production chiplets targeted for the fourth quarter of 2027.
Kirk Saban, who heads product, software and solutions for AMD’s embedded business, pointed to the RF lineup as the natural entry point, citing up to 80 TOPS of digital signal processing, integrated RF converters and gains in size, weight, power and cost. The parts will implement UCIe 1.1, the version AMD co-developed in 2022 with Microsoft, Meta and Qualcomm.
The standard’s next revision, which arrived in mid-2024, added support for 3D stacking schemes that raise connection density and cut power. The move puts Versal on the same interconnect path many AI-era silicon designs are adopting.
