The race to move chip packaging from round wafers to rectangular glass panels is entering a new phase, with the panel format itself becoming the battleground.
Samsung Electronics commercialized fan-out panel-level packaging before any rival, using the technology in mobile and wearable chips, and is preparing to extend it into AI and high-performance computing. Industry watchers say the next stage of panel-level packaging competition may depend less on who moved first than on which rectangular panel size equipment makers, materials suppliers and packaging houses ultimately standardize around.
TSMC’s push toward a 310mm panel format is threatening Samsung’s early lead, according to DigiTimes. The foundry leader has been working on panel-level packaging to complement its CoWoS lines as AI demand stretches conventional round-wafer packaging capacity.
Panel-level packaging promises more chips per substrate and lower cost by using larger rectangular panels instead of round wafers, which waste edge area. Samsung began with its own format, and the industry has yet to settle on a common standard, leaving suppliers to hedge across multiple panel sizes.
The outcome will shape where the next wave of AI accelerator packaging capacity lands, and whether Samsung can convert its head start into a lasting advantage or loses ground to TSMC’s larger ecosystem.
