Applied Materials and Intel are expanding a joint development effort aimed at the parts of a chip that limit AI performance: the wiring and the packaging. The work links Applied’s EPIC Center in Silicon Valley with Intel’s R&D campus in Hillsboro, Oregon.
What the teams will build
The collaboration covers next-generation materials, process technology and device structures for advanced logic nodes. It spans both the front end, where transistors are formed, and the back end, where interconnects are laid down, with interconnect scaling as an explicit target.
The pair will also work on advanced packaging for Foveros-based 3D stacking, the technique Intel uses to bond logic dies vertically. Specific goals include higher interconnect density plus better power delivery and thermal behavior.
Why packaging is the new battleground
As transistor shrinks slow, moving data between and within dies has become the binding constraint on AI accelerators. Intel is a founding partner of the EPIC Center, a facility Applied designed to shorten the path from lab result to high-volume manufacturing.
“The demand for AI computing is driving the need for major advances in performance, power efficiency, and packaging,” said Lip-Bu Tan, Intel’s chief executive.
Applied said the center is scheduled to be operationally ready this year. Both companies framed the work as a way to cut development cycles while keeping advanced output in the United States.
