A research paper from SK hynix and university partners argues that packing optical engines into chip packages is the way past the data-movement limits now pinning AI systems. Published on August 20 in Nature Electronics, the study maps a development path for co-packaged optics, or CPO, and sets performance targets for next-generation AI infrastructure.
The strain shows in the numbers behind AI clusters. Interconnect bandwidth has grown only about 1.4 times over two years. Compute, by contrast, roughly triples on the same clock. Copper wiring cannot close that gap: signals lose strength over distance, and the correction circuits that fix them add power, heat and latency. High-bandwidth memory relieves pressure inside the accelerator package, but the wall reappears at system scale, where thousands of GPUs and HBM stacks must exchange data.
CPO places optical transceivers in the same package as processors, letting chips exchange data with light. The researchers set targets of more than 100 terabits per second per node, energy use below one picojoule per bit and low chip-to-chip latency. The long-term vision is an optics-centric architecture that extends light connections all the way to memory interfaces, directly linking memory and processors.
SK hynix says optical interconnects are still early in industrialization, with challenges from low-power optical devices to signal protocols. The company is approaching memory from a system perspective, a shift it argues will matter as AI competition moves from chips to whole systems. The paper’s corresponding authors are Seunghoon Hong, who leads AI infrastructure planning at SK hynix, and Kyu Sang Lee of the University of Virginia.
