Siemens and Samsung Foundry have deepened their engineering collaboration to qualify Siemens’ EDA tools across Samsung’s advanced process nodes, targeting improved design quality and first-pass silicon success for the global fabless ecosystem.
Expanded photonic verification
The partnership now extends to photonic integrated circuit (PIC) verification, addressing growing complexity in photonic designs. Siemens’ Calibre software enables equation-based design rule checking, curvilinear layout versus schematic verification, and advanced pattern matching. These capabilities ensure accurate verification of complex curvilinear geometries within Samsung’s process flows, supporting manufacturable PIC designs.
Physical verification and power integrity
Calibre nmPlatform tools—including nmDRC, nmLVS, PERC, xACT, and DesignEnhancer—are fully qualified for Samsung Foundry processes. To tackle escalating power integrity challenges, Samsung plans an official release of Calibre DesignEnhancer Pge for its 2nm node. This tool automates power-grid enhancement, mitigating electromigration and IR drop issues through intelligent layout optimization, supporting a shift-left methodology that boosts engineering productivity and design reliability.
Design-for-test and yield analysis
Siemens’ Tessent design-for-test portfolio enables scalable DFT methodologies for advanced-node yield analysis. Joint work focuses on defect-oriented test strategies and physical failure analysis to reduce defective parts per million. A key milestone is the establishment of a high-resolution chain diagnosis reference flow using Tessent HiRes Chain Diagnosis, enabling cell-aware, layout-aware, and silicon-proven global signal diagnosis for improved failure isolation.
Advanced packaging and 3d IC integration
Samsung Foundry has adopted Siemens’ Innovator3D IC tools for its 2.3D Cube-E advanced package platform. Innovator3D IC Integrator supports early-stage floorplanning and rapid design changes, while Innovator3D IC Layout automates daisy-chain netlist generation for designs exceeding two million pins. Comprehensive physical verification via Calibre 3DStack ensures design integrity for complex 2.5D and 3D IC implementations.
Analog, RF, and digital implementation
Siemens’ Solido Simulation Suite is qualified for SPICE-accurate verification across Samsung’s process technologies, including first-time qualifications for automotive applications on 4nm and 2nm. Solido SPICE and Analog FastSPICE enable aging and reliability analysis through Open Model Interface support from 14nm to 2nm. In digital implementation, Aprisa software is fully certified for Samsung’s leading-edge nodes, optimizing performance, power, and area to accelerate design closure.
This collaboration positions Siemens and Samsung Foundry to address escalating design complexity across photonics, power integrity, test, packaging, and analog domains, reinforcing a production-ready EDA ecosystem for next-generation silicon. As chip designs push toward 2nm and 3D integration, the alignment of proven EDA tools with advanced process platforms will be critical for fabless customers seeking faster time-to-market and higher first-pass success rates.
