CXMT used the Integrated Circuits and Chiplet Conference in Hefei to detail a 4F2 DRAM architecture, with a next-generation DDR5 server module targeted for launch before the year ends.
Today’s DRAM cells occupy 6F2, meaning six times the square of the minimum feature size. Cutting that to four could raise density within the same area by 30 to 50 percent, according to analyst summaries of the disclosure.
At the centre sits a vertical surrounded gate transistor, which the company says improves electrostatic control while reducing leakage and short-channel effects.
The design leans on 3D techniques to sidestep conventional scaling limits, separating the cell array from peripheral CMOS fabrication and using wafer-level hybrid bonding for high-speed connections.
President Cao Kanyu said the company holds more than 300 published patent families tied to the approach and called the portfolio industry-leading.
The commercial backdrop gives the claim weight. TrendForce puts CXMT fourth in global DRAM revenue for the second quarter, with share rising to 9.5 percent from 7.6 percent, behind Samsung, SK hynix and Micron.
Samsung has shown a 4F2 prototype with wafer-to-wafer bonding but is prioritizing hybrid bonding first, and the technology is not expected on the market before 2028.
That gap is CXMT’s opening. Announcing a launch is not the same as shipping in volume, and the company still faces equipment restrictions that could slow any ramp.
