AI chips are running into a wall where they cannot fit enough fast memory beside the compute, and the HBM stacks bolted to the side of accelerators are straining to keep up. NEO Semiconductor, a San Jose startup, is pitching two designs it says attack both sides of that squeeze at once.
One is X-SRAM, built for the space directly on the processor. NEO claims five times the density of conventional SRAM at SRAM-class speeds, aimed at nanosheet CMOS nodes and, eventually, monolithic 3D integration so accelerators can carry far more cache.
The second design, 3D X-DRAM, stacks memory cells the way 3D NAND flash does, and NEO reckons that approach can lift DRAM capacity as much as tenfold. Feeding HBM towers of that scale, the company argues, would ease the memory pressure on training and inference runs, though a proof of concept is done and production dates are not set.
CEO Andy Hsu framed the pairing as a way past the AI memory wall where cache and HBM limits throttle performance, and the company presented the work at the Future of Memory and Storage conference in Santa Clara this week. DigiTimes reports NEO is hunting a manufacturing partner to commercialize X-SRAM by the end of 2026, alongside a portfolio that also includes X-HBM, X-NAND and 3D X-AI designs.
