IBM and Siemens announced a research collaboration on October 14 aimed at the design and manufacturing problems that come with stacking transistors vertically.
The work targets IBM’s nanostack architecture, which places an NFET and a PFET on separate wafers and bonds them into a single stacked structure. IBM has said the approach delivers roughly 50 percent logic area scaling against a 2nm node.
Siemens brings its EDA toolchain to the effort, covering how such devices get modeled, placed and verified. Stacked transistor schemes break several assumptions baked into conventional design flows, including where heat travels and how timing behaves when the two device types sit on top of each other.
IBM has positioned nanostack for the generation beyond nanosheet, sometimes described as the 7 angstrom node. The two firms have not disclosed a timeline for commercial deployment.
The deal follows a broader pattern of research houses pulling in tool vendors early, as the cost of getting physics wrong at these dimensions has made late-stage design fixes untenable.
