SK hynix has posted job listings in San Jose for engineers to co-develop 3D-stacked DRAM-on-Logic products alongside an unnamed US partner, signaling that the memory maker is moving beyond HBM into architectures purpose-built for on-device AI. The positions, listed through its American subsidiary, call for specialists who can lead logic-die co-design with a customer already engaged on the project.
The 3D-stacked DRAM-on-Logic approach places memory cells directly above a system-on-chip using advanced bonding techniques, cutting interconnect distance and widening data channels compared with conventional package-on-package layouts. For smartphone application processors from Apple and Qualcomm, that translates to lower power draw and higher bandwidth for running AI inference locally. SK hynix Chief Development Officer Hyun Ahn flagged the memory bandwidth bottleneck at TSMC’s Technology Symposium earlier this year, arguing that incremental advances would not meet the demands of edge AI workloads.
The US hiring push aligns with SK hynix’s broader roadmap, which already includes TSMC collaboration on HBM4 base dies and plans to extend that partnership into 3D-stacked architectures and high-bandwidth flash. The decision to post dedicated 3D-stacked DRAM roles for the first time and pair them with a specific customer suggests the company has moved from research into an active development program. Meanwhile, Samsung is pursuing its own monolithic 3D DRAM path through a joint simulation-stage study with imec, KU Leuven, and Lam Research, though no commercialization timeline has been disclosed.
