Samsung used a pre-briefing ahead of the Future of Memory and Storage Summit to lay out a 3D memory roadmap built to smash what it calls the digital memory wall. Leno Park, vice president of flash solutions, said AI infrastructure is straining to deliver roughly 100 tokens per second per user today, and the company is planning for 1,000 tokens per second per user by 2030.
HBM4E is now in sampling with ecosystem partners evaluating the devices. The design uses a 4nm base die, roughly 4x more through-silicon vias and advanced packaging with more than 300,000 microbumps. Samsung expects HBM to account for more than half of DRAM sales by 2030, and is targeting HBM5 with a 2nm gate-all-around base die.
The headline concept is zHBM, which moves from the current 2.5D side-by-side layout to a true 3D structure with the AI accelerator placed directly over the HBM stack. Shortening the distance data must travel should improve bandwidth and power efficiency while cutting thermal constraints. Samsung claims zHBM could deliver roughly 8x the performance of HBM5, more than 10x the memory density, 3x the energy efficiency and less than half the thermal resistance, though the gains require close co-design with accelerator partners.
Alongside zHBM came zNAND-O, a NAND concept aimed at edge AI. The architecture shortens the distance between processor and memory and builds on the 10th generation of Samsung TLC V-NAND, which the company says will exceed 400 layers with an 11 percent lateral shrink and roughly 58 percent higher memory density.
A new heat pipe block, described as a chimney over hot spots, is meant to cool the HBM stacks. Park said conventional architectures cannot keep up with growing AI models, and that after 2029 the industry will need a structural breakthrough rather than another routine speed bump.
