Google has gone from releasing a TPU every two years to two in the past year, and its chief technologist says the cadence could accelerate further. Amin Vahdat told SEMICON Taiwan that the chip’s rollout rhythm shifted from biennial to annual and then doubled again, and that pushing the pace higher means Google’s custom-silicon delivery engine must speed up along with it.
Vahdat described manufacturing lines running at full speed with testing capacity in place, but warned that the supply chain is the binding constraint. He listed memory, printed circuit boards, high-voltage power supplies, liquid cooling and AI racks as recurring bottlenecks, and said the way Google works with its supply chain will undergo radical change because constraints shift from week to week.
The scale behind those demands is enormous. Google builds networking into every accelerator, co-locating compute and switching for efficiency, and ties its data centers together over a wide-area network that can run roughly a million TPUs in tandem, from a superpod cluster at the 10,000-chip level up to a data center network at 100,000 and the interlinked facilities beyond.
The faster rhythm is part of a broader spending surge. Alphabet raised its 2026 capital spending guidance to between $195B and $205B to build out next-generation AI data centers, and each TPU generation consumes more of that budget in memory, power and packaging. For suppliers, Vahdat’s message was blunt. Design cycles measured in years no longer match the deployment cycles Google now expects.
