Faults buried deep inside multi-die AI packages are forcing South Korea’s chip test industry to rethink how it inspects, diagnoses and repairs expensive hardware.
At a Suwon conference on Aug. 26, Hanyang University professor emeritus Park Sung-joo argued that testing can no longer stop at the chip edge. He called for a unified view of the whole chain, from automated test equipment and connectors to printed circuit boards, probe cards and pogo pins, urging companies to standardize across every link.
The stakes are rising because AI processors now bundle GPUs, high-bandwidth memory and power management dies into a single package. HBM stacks link DRAM layers with through-silicon vias and ride silicon interposers next to compute dies, and researchers are already proposing vertical structures that stack memory above the GPU itself.
Every added connection adds failure points. Opens, shorts and other defects can hide in microbumps, vias or interposer traces, and discarding a finished package for a single bad link is too costly. Park said the industry needs precise diagnosis plus redundant paths that reroute signals around damaged connections, pointing to repair mechanisms built into the UCIe standard and fault-detection rules in IEEE 1500.
Around 50 domestic and overseas firms are now cooperating through the Institute of Semiconductor Test of Korea on common specifications. Memory testers, once split by maker-specific commands and clocks, and probe card components such as relays and switches are among the areas being harmonized.
