TSMC researchers have shown a way to keep atom-thin transistors on the scaling roadmap, engineering an interface layer just 0.42 nanometers thick that protects electron transport in molybdenum disulfide devices.
Silicon transistors are approaching physical limits that make each new generation harder to shrink. Two-dimensional semiconductors such as monolayer MoS2 offer a route forward because their channels can be just one atomic layer thick, but their practical performance has been held back by the interface between the channel and the gate dielectric. Deposited materials nucleate poorly on the van der Waals surface, creating gaps and defects that increase leakage and scatter carriers.
A team from National Yang Ming Chiao Tung University and TSMC Corporate Research treated that interface as an engineered device layer rather than a passive boundary. They deposited an ultrathin epitaxial aluminum film on CVD-grown monolayer MoS2, then oxidized it to form roughly 0.42 nanometers of aluminum oxide. A high-k hafnium oxide dielectric was added on top.
The oxidized aluminum supplies a smooth, continuous surface for the hafnium oxide and acts as an atomic-scale buffer against damaging interactions with the semiconductor. With total equivalent oxide thickness near one nanometer, short-channel top-gate transistors reached a maximum transconductance of 0.45 millisiemens per micrometer at channel lengths near 100 nanometers, with low gate leakage and minimal hysteresis.
The work points toward thinner dielectrics and lower operating voltages for future 2D-material transistors, a step that could matter for power-efficient chips beyond silicon.
