RISC-V International announced at the RISC-V Summit Europe 2026 in Bologna that its open-standard instruction set architecture has reached server maturity, positioning it to disrupt data centers, edge AI, and space exploration markets.
Market momentum
RISC-V could capture 33.7% of all hardware segments by 2031, according to SHD Group. Edge computing and data center markets alone are projected to exceed $45 billion and $70 billion respectively by decade’s end. Startups SiFive and Axelera have raised $650 million combined, while Microsoft has joined RISC-V International’s top board.
Server platform standardization
The ratification of the RISC-V Server Platform Specification 1.0, based on the RVA23 profile ratified in 2024, marks a critical inflection point. The spec brings industry-standard boot systems and runtime services—including UEFI and ACPI 6.6 support—directly to RISC-V hardware, ensuring consistent system software operation across heterogeneous servers.
This standardization has triggered what the organization calls “the year of RVA silicon.” Companies are launching server-class processors including SiFive’s Performance P870D with up to 128 cores, Akeana’s Alpine Test Chip, and NextSilicon’s Arbel server-grade CPU. Epic Semi’s Contrail AIX superchip blends 32 RISC-V cores with 16 AI cores, delivering up to 75 TOPS.
For hyperscalers, RISC-V offers a viable alternative to proprietary ARM and x86 architectures, reducing single-vendor lock-in risk. Canonical’s Ubuntu 26.04 LTS now fully supports RVA23, easing enterprise management of mixed-architecture data centers.
Physical AI at the edge
RISC-V’s advanced vector and matrix extensions enable “physical AI”—systems that not only infer and decide but also act in the real world. By running complex AI algorithms on the same core that handles control software and the OS, the architecture eliminates the need for data and weight transfers to a separate neural processing unit. This avoids “memcopy,” a process that introduces latency and increases power consumption.
The power efficiency advantage is already demonstrated in production: a humanoid robot using SpacemiT’s K3 RISC-V processor completed a half-marathon in Beijing. In Brazil, São Paulo University researchers are using battery-powered RISC-V microcontrollers to build an “Internet of Trees” mesh network that detects illegal logging and forest fires.
Space exploration adoption
The aerospace industry is pivoting from legacy SPARC-based architectures to RISC-V for radiation- and fault-resistant spaceflight computers. The RISC-V Space Special Interest Group, chaired by the European Space Agency and E4 Computing, brings together NASA, Microchip, SiFive, and Frontgrade Gaisler to define standards for lunar landers, satellite cloud processing, and workload isolation.
Major hardware projects are underway: NASA is testing a high-performance spaceflight processor with Microchip and SiFive, while the European Commission’s COSMIC7 project is building a 7-nm RISC-V chip for orbital use. Frontgrade Gaisler is transitioning from SPARC-based LEON processors to RISC-V-based NOEL chips, citing the open architecture’s transparency as essential for safety certifications.
Forward outlook
RISC-V has evolved from a niche microcontroller architecture into a mature platform with ratified server specifications, validated edge AI deployments, and active space-grade hardware programs. The combination of open standards, growing commercial investment, and government interest in digital sovereignty positions RISC-V as a structural alternative to proprietary incumbents across the full computing spectrum—from terrestrial data centers to orbital systems.
