Researchers in South Korea and the US have demonstrated a way to stack ten chips, each about 14 micrometers thick, in a single pass, claiming integration density roughly four times higher than today’s HBM.
The process, developed by POSTECH, the Korea Institute of Industrial Technology and Texas A&M University, combines transfer printing with in-situ bonding. Chips are placed precisely and metallic bonds form during the transfer step under low temperature and low pressure, so placement and interconnection happen at the same time.
The collaborators report that alignment drift stayed minimal across repeated stacking passes and warpage was held in check. The findings appear in Results in Engineering and point to denser options for AI accelerators and next-generation memory.
Seok Kim, a POSTECH mechanical engineering professor, said the stacks achieve integration density roughly four times that of today’s HBM and could serve as a building block for high-performance AI semiconductors and next-generation memory systems.
The work arrives as the industry hunts for ways around a persistent HBM shortage that has pushed memory vendors to expand fabs and customers to redesign chips around whatever capacity they can secure. Stacking more dies in the same footprint is one route to raising capacity without stretching wafer supply.
Scaling the method to production volumes is the remaining hurdle, but the researchers see their transfer-and-bond approach becoming a foundation for the stacked memory that AI hardware will demand later this decade.
