Synopsys, Cadence and Siemens push chip design toward full autonomy at DAC 2026

All three major EDA vendors unveiled long-running agentic workflows that promise dramatic speedups in chip verification and design.

ChipNews Staff
2 Min Read

The 2026 DAC Chips to Systems Conference marked a turning point for electronic design automation as Synopsys, Cadence, and Siemens each announced fully autonomous agentic workflows for chip and system design, all built on NVIDIA’s agentic AI stack.

Synopsys unveiled a fully autonomous design verification agent that orchestrates the entire chip verification cycle, claiming up to 50x faster time-to-validated RTL with a 20 percent additional coverage improvement. The company also introduced its first fully autonomous CAE workflow for thermal analysis using Ansys Icepak. Separately, Synopsys announced the first autonomous EDA workflows on Microsoft Discovery, developed with Microsoft and actively evaluated by AMD.

Cadence introduced the AuraStack AI Super Agent for PCB and advanced packaging design, citing up to 20x faster multiphysics performance. The new agent completes Cadence’s portfolio of four AI Super Agents spanning silicon to system design, which the company calls the industry’s first complete agentic stack.

Siemens expanded its partnership with NVIDIA around self-verifying agentic workflows in its Fuse EDA AI Agent system. The company reported more than 10x faster library characterization in the Solido Characterization Suite with a 5x to 10x reduction in token costs.

NVIDIA anchored the announcements by expanding its Agent Toolkit with PhysicsNeMo and CUDA-X libraries, while reporting that its Vera CPU is being deployed across internal EDA workflows with vendor-reported 1.5x gains on Synopsys VCS and Cadence Jasper.

Share This Article