The memory die slated for SK hynix’s HBM4E stacks is pulling its production strategy forward. The company intends to make sixth-generation 10nm-class DRAM, tagged 1c, its main process early next year, a step it needs before HBM4E volume output begins in 2027. Early samples of that memory went to customers in July.
Ramp data shows the mix changing quickly. The 1c node supplied about 10% of SK hynix wafers in Q1 and 13% in Q2, versus roughly 16% at Samsung and 19% at Micron. Figures reported through TrendForce put the share at about 24% in the current quarter and 34% by Q4, when Samsung is expected to sit near 31%. The crossover arrives in early 2027, with SK hynix projecting 35% for 1c as 1b fades to 33%.
The two Korean memory leaders diverged on HBM4. Samsung put 1c dies under its stacks to reach speeds close to 11.7Gbps, while SK hynix stuck with proven 1b silicon and MR-MUF packaging to hold yields and volume. SK hynix argues the denser node lowers cost per bit as more die fit on a wafer, though qualification timing will decide how much of that advantage shows up in its second-half results.
Both memory makers have already penciled dates for the seventh-generation node, tagged 1d, which will follow 1c into the fabs. SK hynix does not expect its development work on that node to finish until December. Samsung, moving faster, aims to complete its own version this month and to reach initial production lines by late 2027, with HBM5E-era memory to follow near the start of the next decade.
