Micron has named the process that comes after its 1-gamma DRAM. The new one is 1-delta, built with angstrom-level process control and a high-k metal gate structure, and it should pack about 25 percent more bits per area than the node it replaces. Volume output begins in the second half of 2027.
What rides on the node matters more than the density number. Both DDR6 and LPDDR6 are supported, and Micron frames the first of those as memory for AI servers of the high-reliability kind rather than the natural upgrade path for a desktop or laptop on DDR5. Neither standard has a launch date.
Capacity is where the pitch gets loud. A 512GB DDR5 module ran at 9,200MT/s in a September demo; the successor generation is said to reach one-terabyte modules, which the company calls the highest-capacity part of that type anyone will have in production. LPDDR6, meanwhile, is claimed at 35 percent better power efficiency than LPDDR5, and better still at certain densities. Scott DeBoer, president and chief technology and products officer, put Meta among the partners working to bring that mobile standard into data centers.
One road is shut. Future memory will sit on a six-square cell layout, not the four-square design rivals are chasing, because of cost, complexity and capacitor pitch limits. Wafer bonding and High-NA lithography come first, then new materials, and a design stacking memory directly atop the compute die is pitched on bandwidth per watt.
Storage gets a generation too: G11 flash passes 400 layers, aims at double the bit density of G9, 1.5 times the input-output speed and over 25 percent less energy per transfer, again for the second half of 2027.
