Every generation of AI accelerator packs more compute dies and more memory stacks into one package, and somebody has to build the substrate underneath. Korea’s component makers want that business, and they are betting the answer will not always be TSMC’s CoWoS.
For now the incumbent looks unassailable. Analysts expect the CoWoS-L format to hold the mainstream slot for AI packaging well into the late 2020s, helped by TSMC’s production experience and the fact that Nvidia and its peers need the technology to pair logic with HBM. Nobody is predicting a fast handover.
The gap opens on cost and scale. Older package designs carried a full silicon interposer. The current approach spends silicon only where the connections demand it, which lets designs grow larger without the whole structure growing expensive. As accelerators get hungrier for power, customers have started shopping for other routes.
That is the opening Samsung Electro-Mechanics and LG Innotek are working. Both are building out advanced substrate capability, including technology tied to Intel’s embedded multi-die interconnect bridge, or EMIB, which gives chip designers a different way to link multiple dies.
