Export controls have kept the country’s most advanced production on deep ultraviolet tools, and a new device architecture is being offered as a way around that ceiling.
The Chinese Academy of Sciences has reported gate-all-around transistors built on those machines.
The devices show on-off ratios above 500,000, meaning current in the conducting state dwarfs leakage by that factor. A gate wrapping the channel gives tighter control than the fin-shaped design it replaces.
Because the new transistors tolerate a looser fin pitch, multi-patterning steps could be relaxed while density is preserved by shrinking cell height, from five metal tracks down to four.
Analysts reading the work place the practical outcome at 5nm-equivalent performance rather than 3nm.
The obstacle is middle-of-line processing, the contact and routing layers that sit between transistors and wiring. Their pitch does not improve when the transistor is redesigned, so the cell can only shrink so far.
Immersion DUV with repeated patterning has already delivered 7nm-class circuits. Going below that without extreme ultraviolet light is the central problem the industry has watched for years.
If the approach holds up in volume, its value is defensive: domestic designers could keep pace without imported scanners.
Yields, costs and equipment availability are unreported, and no production timeline has been given.
