Chinese fabs locked out of EUV lithography may have gained a route to next-generation DRAM, with toolmaker Naura Technology Group publishing an etch technique built for vertical memory stacks.
3D DRAM packs cells by alternating silicon with silicon-germanium layers and later removing the SiGe, leaving channels where word lines, bit lines and gates are deposited. Western export rules keep Chinese plants on deep-ultraviolet tools, whose resolution caps how densely circuits can be laid out horizontally, so the industry has been searching for ways to build upward instead.
In a paper carried by an IEEE publication, Naura engineers describe a cyclic two-step process. Neutral fluorine radicals first attack the germanium-bearing layers, and a protective film forms on the silicon surfaces so they stay intact. A plasma-assisted purge then clears residue from the bottom of the deep stack, attacking the uneven etching that has limited earlier attempts.
Naura reports a silicon-to-SiGe etch selectivity greater than 500 to 1 across a 200nm gap, meaning the sacrificial material is consumed hundreds of times faster than the silicon that becomes the device. It touts the result as an answer to the depth uniformity and byproduct buildup problems that plague high-aspect-ratio memory etches.
The likely first customer is CXMT, China’s leading DRAM producer, which already ships small volumes of HBM and keeps gaining commodity DRAM share. A workable vertical-memory flow would reduce its dependence on sanctioned lithography, echoing Huawei’s LogicFolding plan to stack logic circuits rather than shrink them.
