Synopsys has updated its CXL IP portfolio for the AI era, rolling out what it describes as the first complete CXL 4.0 IP solution for memory connectivity.
The lineup spans controllers, PHY and verification IP built around the CXL 4.0 specification, which doubles link bandwidth over earlier versions through PAM4 signaling. The target is AI infrastructure, where accelerators and servers need fast, coherent access to pools of expanded memory.
CXL has become the interconnect of choice for memory expansion and disaggregation as AI workloads outgrow the memory attached to individual processors. Chipmakers and system builders are weighing CXL-based memory tiers to stretch capacity without paying for more DRAM than they can put to work.
The portfolio update lands as Synopsys pushes its multi-die and AI-era infrastructure roadmaps, giving designers a single IP stack for CXL-based memory systems instead of patching together pieces from multiple vendors.
