Peking University has prototyped an electronic design automation (EDA) tool purpose-built for Huawei’s LogicFolding 3D chip architecture, claiming a 30% reduction in internal wire length in early tests.
True-3d design approach
The tool, developed by the university’s School of Integrated Circuits, treats a multilayer chip as a single vertical structure rather than designing each layer in 2D and stacking them afterward. This “true-3D” methodology optimizes inter-layer routing simultaneously, compressing signal propagation paths and reducing resistance and capacitance on critical wiring. Researchers reported improvements in both performance and thermal management compared to conventional EDA workflows.
Logicfolding and strategic context
Huawei unveiled LogicFolding and its accompanying Tau Scaling Law at the IEEE International Symposium on Circuits and Systems in Shanghai, two days before Peking University’s announcement. LogicFolding folds traditional 2D circuit layouts into vertical 3D stacks, shortening the physical distances electrical signals travel. The architecture is slated for first commercial deployment in Huawei’s Kirin smartphone processors later this year.
Huawei’s stated goal is to achieve transistor density equivalent to 1.4nm processes by 2031, without access to extreme ultraviolet (EUV) lithography equipment restricted under U.S. export controls.
EDA market dependencies
Synopsys, Cadence, and Siemens EDA command 31%, 30%, and 13% of the global EDA market, respectively, with their combined share within China exceeding 80%. The U.S. imposed and then lifted EDA export restrictions last year as part of a rare-earth materials deal, but the episode underscored Chinese chipmakers’ reliance on Western tools. Domestic EDA firms such as Empyrean Technology and Primarius have made progress in analog and physical verification, but none yet offer a full digital design flow competitive at advanced nodes.
Path to production
Peking University’s prototype addresses a fundamentally different problem than existing 3D IC platforms from Synopsys and Cadence, which focus on integrating separate chiplets within a package. LogicFolding optimizes intra-die vertical stacking at the transistor level, requiring place-and-route tools to work across the full vertical structure simultaneously. However, a university prototype is far from production-grade software. EDA tools require years of development, foundry process design kit integration, and validation across thousands of tape-outs before chipmakers will trust them.
The significance of this development lies not in immediate commercial viability but in its strategic positioning. If Peking University’s tool can scale from prototype to production, it would reduce China’s dependence on Western EDA incumbents and accelerate Huawei’s roadmap to sub-2nm-equivalent nodes under export constraints. Whether the 30% wire-length improvement holds at scale—and whether the tool can achieve the reliability and ecosystem integration required for advanced manufacturing—remains the critical open question.
