The industry has shifted from questioning *if* chiplet architectures will dominate semiconductor design to confronting the practical engineering challenges of scaling them in production.
The New Scalability Imperative
Scaling multi-die systems now requires addressing bottlenecks across interconnect, packaging, power delivery, thermal management, and design complexity. EE Times’ upcoming virtual event, *The Road to Chiplet Scalability*, will convene semiconductor firms, EDA vendors, packaging specialists, and system architects to examine what it takes to build production-ready heterogeneous systems in the AI era.
Accelerating the Design Flow
Day one focuses on how chiplet architectures are reshaping design methodologies and placing new demands on EDA tools. Physical design considerations are moving earlier in the development process, enabling teams to make architectural decisions around partitioning, interconnect, and power delivery sooner. Sessions will explore the increasing complexity of large heterogeneous systems and the challenges of building unified tool flows across dies, packages, and system integration.
Keynote speakers include Stelios Diamantidis, chief product officer at Cognichip, who will discuss AI-driven physics-informed foundation models in EDA. Garrett Wyatt, design manager for data center GPU products at AMD, will address how current EDA toolflows bottleneck chiplet-based designs and share firsthand observations of where multi-chiplet systems are hitting limits. A panel moderated by EE Times senior reporter Sally Ward-Foxton will feature all three major EDA vendors, examining whether current tools can scale with growing multi-die complexity.
Manufacturing and Integration Challenges
Day two examines underlying technologies enabling chiplet scalability, including advanced packaging, 2D and 3D integration, interconnect standards, and system-level implementation. Marvell senior VP and GM Preet Virk will discuss the urgent need for XPU-to-XPU bandwidth and the proliferation of interconnect types creating chiplet variants. A panel moderated by EE Times executive editor Nitin Dahad will explore where scaling limits currently exist and whether silicon photonics or co-packaged optics may become necessary as electrical interconnects approach practical limits.
Beyond the Hype Cycle
Chiplets are entering a phase of maturity, with standards like UCIe evolving, packaging technologies improving, and repeatable methodologies for multi-die integration emerging. However, yield, interoperability, tool flows, thermal density, and system-level reliability remain open challenges. The tension between chiplet promise and practical scaling constraints defines the industry’s current inflection point—and this conference aims to map the path forward.
