TSMC is the world’s most important chip factory. Siemens makes the software that designs those chips. Now they’re putting artificial intelligence in the driver’s seat.
The two companies are deepening a partnership that has been running for years, but this time the focus is on embedding AI directly into the electronic design automation (EDA) workflow. Think of EDA as the CAD software for chip engineers, but infinitely more complex. Siemens is using its new Fuse EDA AI System—a domain-specific agentic AI platform—to automate tasks that have traditionally required hours of manual tweaking.
The AI That Fixes Your Mistakes
One of the most tedious parts of chip design is fixing design rule violations, or DRCs. These are the thousands of microscopic checks that ensure a chip won’t short-circuit or overheat. Siemens’ Calibre software, now paired with TSMC’s latest process nodes, can automatically fix these violations across multiple steps and tools. The result? Engineers stop babysitting the verification flow and start focusing on architecture.
The same AI logic is being applied to digital design cycles via Siemens’ Aprisa software. It gives designers instant access to design data, recommends fixes in real time, and even executes commands directly. It’s like having a senior engineer who never sleeps and never asks for a coffee break.
Hot Chips, Cool Solutions
3D stacking is where chips get really interesting—and really hot. Stacking logic dies on top of memory creates thermal nightmares. Siemens’ Calibre 3DThermal software has now earned TSMC certification for both static and transient thermal analysis. That means designers can simulate exactly how a 3D IC will heat up under load, and adjust power delivery before they ever cut silicon.
TSMC’s 3DFabric technologies also get a boost. Calibre 3DStack now supports alignment checks, inter-chiplet DRC, antenna analysis, and point-to-point resistance extraction. All of these are now expressed in the 3Dblox syntax, making them easier to integrate into existing workflows.
The Node Race
Siemens isn’t just keeping up with TSMC’s bleeding-edge nodes—it’s certified for them. Calibre nmPlatform now supports TSMC’s 3nm, 2nm, A16, and A14 processes. The Solido Simulation Suite is certified for SPICE accuracy on those same nodes, including reliability-aware simulation that accounts for IC aging, self-heating, and safe operating area checks.
Even silicon photonics gets a nod. Siemens tools are now enabled for TSMC’s Compact Universal Photonic Engine (COUPE) technology, covering design, implementation, and verification. That’s a big deal for anyone building optical interconnects for data centers.
What this all means: Chip design is no longer just about shrinking transistors. It’s about using AI to manage the insane complexity that comes with that shrinking. Siemens and TSMC are betting that the next great chip won’t just be smaller—it’ll be smarter to design.
