Samsung is putting its most advanced logic process to work for memory, planning to build the HBM5 base die on a 2nm gate-all-around node to handle the growing thermal and bandwidth demands of AI accelerators. It marks the first time the company pairs its leading-edge foundry process with a high-bandwidth memory product.
The base die is the logic layer that connects stacked DRAM to the processor, routing data through thousands of through-silicon vias. Moving from the roughly 7nm or 5nm nodes used in earlier HBM generations to 2nm GAA delivers lower switching power and tighter transistor packing, both critical as HBM5 targets 50% performance uplift over HBM4E.
Heat has become a first-order design constraint for HBM stacks. Faster data rates generate more thermal load in the interface logic, and the GAA architecture’s improved electrostatic control at reduced voltages helps keep power density in check. Denser TSVs also improve signal integrity at the higher speeds HBM5 demands.
Samsung’s foundry division has been working through 2nm yield challenges, with recent estimates around 50-60% for some designs. The HBM5 base die offers a captive production run that can help validate and mature the process node ahead of external customer commitments. HBM5 is expected to enter volume production in 2027.
