AI-assisted chip design took another step forward this week as Nvidia and Duke University researchers reported a system that repairs layout errors at sub-2nm nodes with far less manual effort.
Their framework, named SCALE, targets design rule violations that emerge during place-and-route, the stage where millions of cells get arranged and wired. At advanced geometries these errors multiply as rules interact and routing layers stack up, and today’s engineers spend long hours untangling them by hand.
The project’s key insight is that language models can learn to understand layouts if the geometry is translated into text. The team serializes multi-layer routing data, then has a model practice reconstructing masked shapes from surrounding context. No labeled violations are needed for this training stage.
At run time, rule descriptions written in natural language steer the model toward candidate layouts that are likely to violate foundry constraints. An industrial signoff checker filters those candidates, and the resulting annotated examples teach a specialized vision model to guide repairs with rule awareness.
On 100 real test cases from sub-2nm designs, covering enclosure, spacing, width, and color-spacing rule types, the method lifted the solve rate of leading automated repair agents by 12 to 25 percentage points, reaching as high as 97 percent.
The work suggests visual layout reasoning is within reach for LLM-based tools, extending their role beyond scripting into the geometric heart of physical design.
