IBM has announced the world’s first sub-1 nanometer chip technology, built on a fundamentally new transistor architecture the company calls NanoStack. The 0.7nm node — also described as the 7 angstrom generation — stacks two complete transistors vertically using wafer bonding, achieving approximately 50% logic area scaling versus the 2nm node.
The NanoStack architecture takes IBM’s previous nanosheet technology and stacks one NFET and one PFET transistor on top of each other. The two transistors are fabricated on separate wafers, then joined through a precision wafer-bonding process — an approach that lets each transistor type be optimized independently for performance or power. A staggered channel design is central to the architecture’s area efficiency.
At the VLSI Symposium, IBM presented SRAM results demonstrating more than 40% cell height reduction compared with state-of-the-art non-stacked cells — the largest SRAM scaling improvement the industry has seen in more than a decade. “The step from 3nm to 2nm, we saw only a few percent,” said Mukesh Khare, IBM Fellow and Vice President of Hybrid Cloud Research. “This achievement of 40% will eventually industrialize itself in AI workflows, which require higher bandwidth and lower latency.”
IBM developed a modified NFET replacement metal gate stack that remains thermally stable when subsequent top-FET processing steps expose it to elevated temperatures. The architecture also opens the door to dual-channel engineering — using silicon for the NFET channel and silicon-germanium for the PFET to optimize carrier mobility independently.
The technology is positioned as a scalable platform rather than a one-generation advance, with IBM’s roadmap projecting continued scaling from 7A through 5 angstrom and 3 angstrom nodes. The 40% SRAM scaling gain is particularly significant for AI accelerator design, where on-chip memory capacity and bandwidth directly impact throughput.
IBM is currently conducting this research at its Albany Nanotech Center and is working with Rapidus, the Japanese foundry bringing IBM’s 2nm nanosheet technology into production. A High NA EUV lithography tool is being installed at the Albany facility for continued process development.
