Imec is presenting a superconducting circuit density record at this week’s Applied Superconductivity Conference. The work centers on a three-layer Josephson junction circuit built from niobium-titanium-nitride, or NbTiN, which reaches 3.8 million junctions per square centimeter, a figure the Belgian lab calls a first for the field.
The structures now go down to 150-nanometer junction sizes, and the team layered three metal levels of low-loss NbTiN wiring that can carry inductors, transmission lines and power-clock resonators. Interconnect lines have also slimmed to 30 nanometers, a width imec says conventional niobium processing cannot approach.
The effort targets a simple problem: CMOS is running out of headroom for the power and data movement demands of high-performance computing and AI accelerators. Superconducting logic promises around 100 times better energy efficiency, 1,000 times higher compute density and 1,000 times more broadcast bandwidth than today’s chips, but old niobium processes could not scale to the densities computing needs.
Imec’s answer is a 300-millimeter CMOS-compatible flow organized around three pillars: process technology, design and EDA enablement, and 2.5D and 3D heterogeneous integration that can co-package superconducting devices with other technologies. Richard Rouse, who directs the program, said the platform opens opportunities beyond HPC and AI in quantum control and readout, neuromorphic computing and single-photon detection.
The lab is courting foundries, hyperscalers and system companies to carry the NbTiN technology from research toward production, betting that superconducting compute can eventually ride existing fab infrastructure.
