Google’s TPU v10 family may get a CPU-heavy variant co-developed with AMD, according to a SemiAnalysis research note circulating this weekend.
The analyst firm says market chatter points to AMD joining a TPU project in the v10 generation, which would mark the chip maker’s first real involvement in a custom AI ASIC effort despite its in-house custom silicon team. SemiAnalysis credits AMD with strong intellectual property in advanced packaging and its SoIC stacking technology, and notes that CPU IP could matter just as much, since Google and its customers keep asking for TPUs that pair accelerators with on-package CPU cores for reinforcement learning.
The CPU angle is the intriguing part. Google’s TPU 8i inference servers already ship one Axion CPU for every two TPUs, a big shift from the seventh generation, where a single Xeon served four accelerators. Some deployments reportedly favor a 1:1 ratio, which would make AI systems far more CPU-heavy than today’s designs.
Given that Broadcom has historically turned Google’s accelerator blueprints into silicon and Google itself holds deep architecture expertise, a conventional TPU design job seems unlikely. More plausible is that AMD contributes pieces Google cannot easily source elsewhere, such as CPU blocks, interconnect IP, or advanced packaging know-how.
Neither Google nor AMD has confirmed the talks, and the scope of AMD’s role remains unclear. If the report is accurate, the bigger story may be a TPU tuned for reasoning and agentic workloads, with AMD supplying some of the building blocks.
