Cadence Design Systems has launched AuraStack, an AI-powered “super agent” that designs printed circuit boards and chip packages from natural language descriptions, extending the EDA giant’s push to automate more of the engineering workflow.
The tool lets engineers describe their design goals in plain language, then plans and executes the work using Cadence’s existing software to lay out and virtually test circuit designs. Cadence said AuraStack can cut time to market by up to half and boost productivity on individual tasks as much as 15-fold.
In a demonstration, Cadence showed an engineer using the tool to rework a 5G smartphone circuit board for a cheaper market variant. AuraStack recommended consolidating components for a 28% cost saving and found a lower-cost power management chip compatible with the design.
“The bottleneck isn’t automation. It’s really engineering intelligence,” said Michael Jackson, Cadence’s corporate vice president and general manager for system design and analysis.
Cadence named NVIDIA, TSMC, and Schneider Electric among early users. Customers can pair AuraStack with their choice of AI models including OpenAI’s ChatGPT, Google’s Gemini, or Anthropic’s Claude. Pricing follows a consumption-based model tied to how hard the AI works.
AuraStack follows Cadence’s February 2026 launch of an AI agent for chip design itself. The new tool will roll out in September 2026 and still requires Cadence’s underlying OrCAD and Allegro tools for execution.
